The use of indium bumps in flip-chip bump bonding for high-density interconnection in integrated circuitry, such as between infrared detector arrays and signal-processing modules, is well known. Indium bumps 30 to 40 microns in diameter and spaced approximately 100 microns apart are typically formed in arrays upon two integrated circuit substrate surfaces to be electrically connected such that the indium bumps will fuse when brought into contact and forced together. Each indium bump is connected to a conductive conduit which provides electrical communication to integrated circuitry formed upon the substrate. For example, infrared detector arrays containing a number of detector pixels (e.g. 8.times.128 or 64.times.64) are often formed upon one semiconductor substrate and must be electrically connected to signal conditioning electronics formed upon another semiconductor substrate.
The indium bumps are conventionally formed upon the substrate surfaces by either electroplating or vapor deposition. A photo resist process is used to delineate the indium bumps. In practicing this process the yield for bumps formed near the perimeter of the substrate is typically lower than that for bumps formed near the center. This is due to difficulties which occur during the lift-off process.
Because of the difficulty of bonding the malleable indium directly to the substrate surface, conductive metal pads are first formed thereon. Very tight alignment tolerances (e.g. within +/- 5 microns) must be maintained in the bump formation process to assure that the bumps are properly positioned upon the metal base pads. Proper positioning is achieved through precisely aligning a mask to be used in the photoresist process. Thus, proper alignment of the mask is crucial to the positioning of the bump relative to the base pad. Problems occurring during the bump formation process further reduce the yield. Thus, the overall yield of the indium bump contact formation process is very low.
Some tolerance for slight misalignment of the malleable layer to the base layer must be provided in the prior art since it is not possible to exactly align the mask during the malleable layer formation process. This tolerance is achieved by forming each malleable layer somewhat smaller in area than its corresponding conductive base pad. Thus, a slight misalignment will not cause the malleable layer to overhang the base pad and be partially formed directly upon the substrate. This margin for alignment error thus makes alignment slightly less critical, but it also reduces the surface area of the malleable layer and thus increases the probability of slipping.
Therefore, because of their limited surface area, prior art contact bumps are susceptible to slippage during flip-chip bump bonding. Slippage may occur when two similar-sized bumps are imperfectly aligned. Imperfect alignment results when the bumps are not faced center-to-center during the bump bonding process. Slippage results in poor contact of those indium bumps which fuse and can result in lack of contact among some bumps due to alignment tolerances. That is, the slippage results in an overall misalignment, thus making the alignment of each individual bump particularly crucial. It is possible that the overall misalignment may cause one or more contact bumps to be sufficiently misaligned such that no contact is made at all.
Although such prior art indium contact bumps have proven generally suitable for their intended purposes, they possess inherent deficiencies which detract from their overall effectiveness in the marketplace. In view of the shortcomings of the prior art, it would be desirable to provide a method for forming bump contacts which is simple to practice and which has a higher yield than contemporary processes. It would also be desirable to provide a process for fabricating indium contact bumps having a greater surface area than prior art bump contacts without increasing the overall size of the array.